The technical field of this invention is control of cache memory in data processors and particularly programmer control of invalidation or flushing of selected parts of a second level cache in a digital signal processor.
Data processing systems typically employ data caches and instruction caches to improve performance. A small amount of high speed memory is used as the cache. This cache memory is filled from main memory on an as needed basis. When the data processor requires data or an instruction, this is first sought from the cache memory. If the data or instruction sought is already stored in the cache memory, it is recalled faster than it could have been recalled from main memory. If the data or instruction sought is not stored in the cache memory, it is recalled from main memory for use and also stored in the corresponding cache. A performance improvement is achieved using cache memory based upon the principle of locality of reference. It is likely that the data or the instruction just sought by the data processor will be needed again in the near future. Use of cache memories speeds the accesses needed to service these future needs. A typical high performance data processor will include instruction cache, data cache or both on the same integrated circuit as the data processor core.
Cache memories are widely used in general purpose microprocessors employed in desktop personal computers and workstations. Cache memories are frequently used in microprocessors employed in embedded applications in which the programmable nature of the microprocessor controller is invisible to the programmer. Caching provides a hardware managed, programmer transparent access to a large memory space via a physically small static random access memory (SRAM) with an average memory access time approaching the access time of the SRAM. The hardware managed and programmer transparent aspect of cache systems enables better performance while freeing the programmer from explicit memory management.
Cache memories are typically not used with digital signal processors. Digital signal processors are generally used in applications with real time constraints. Such real time constraints typically do not operate well with cache memories. When employing cache memories the access time for a particular instruction or data cannot be predetermined. If the sought item is stored in the cache, then the access time is a known short time. However, if the item sought is not stored in the cache, then the access time will be very much longer. The determination of hit or miss is controlled by the cache autonomously, but is generally unknown to the programmer without extensive analysis of the access patterns of a particular code segment. Furthermore, since the state of the cache controls the events performed by the cache, it may be necessary to analyze complete systems and long sequences of events in order to predict and control the operation of said cache. Additionally, other demands for main memory access will make the access time from main memory vary greatly. This variation in memory access time makes planning for real time applications extremely difficult or impossible.
In some systems, it is highly desirable to provide a level of control to the programmer over cache operations. For example, it may be necessary for a cache system to support a writeback mechanism, whereby the programmer can direct the cache to write data in the cache back to external memory for shared access by another processor, which doesn""t have access to the cache. Similarly, it is often desirable to be able to clear or invalidate cache entries so that new data can be accessed at addresses which have been updated in the reference memory.
Many caches provide some level of the above functionality. Such functions are normally implemented as a set of control registers, either within the central processing unit or addressable as memory mapped control registers. Typically, writeback and invalidate mechanisms take the form of a control bit, or address register whereby the programmer can force the writeback and/or invalidation of a particular cache line or possibly a cached address from the cache. These known techniques typically make programming programmer directed cache operations difficult and tedious.
This invention enables a program controlled cache state operation on a program designated address range. The program controlled cache state operation could be writeback of data cached from the program designated address range to a higher level memory or such writeback and invalidation of data cached from the program designated address range.
A cache operation unit includes a base address register and a word count register. These registers are loadable by the central processing unit. The program designated address range is from a base address stored in the base address register for a number of words of corresponding to word count register. In the preferred embodiment the program controlled cache state operation begins upon loading the word count register.
The cache operation unit may operate on fractional cache entries. In the embodiment the cache operation unit includes a two""s complement unit. This two""s complement unit forms the two""s complement of M least significant bits of the base address register, where each cache entries has 2M data words. A least number selector produces an output equal to the least of this two""s complement, the word count 2M. The base address register is incremented by the least number selected and the word count register is decremented by this same least number select. The cache state control operations ends when the word count reaches zero.
The cache operation unit may operate only on whole cache entries. The base address register increments and the word count register decrements by the cache entry size. The cache state control operations ends when the word count reaches zero.